Marantz N1G Service Manual download pdf (Page 16)

Reset - RST

Pin 1, Input

Function:

The device enters a low power mode and all internal state

machines registers are reset when low. When

high, the device will be in a normal operation mode .

RST DESCRIPTION

0 Enabled

1 Normal operation mode

Digital Ground - DGND

Pins 6 and 9, Inputs

Function:

Digital ground reference.

Digital Power - VD

Pins 7 and 8, Input

Function:

Digital power supply. Typically 5.0 to 3.0 VDC.

Master Clock - MCLK

Pin 10, Input

Function:

The master clock frequency must be either 256x, 384x, 512x or

768x the input sample rate in Single

Speed Mode; either 128x, 192x 256x or 384x the input sample

rate in Double Speed Mode; or 64x, 96x

128x or 192x the input sample rate in Quad Speed Mode. Tables

4-6 illustrate the standard audio sample

rates and the required master clock frequencies.

Sample

Rate (kHz)

MCLK (MHz)

256x 384x 512x 768x

32 8.1920 12.2880 16.3840 24.5760

44.1 11.2896 16.9344 22.5792 33.8688

48 12.2880 18.4320 24.5760 36.8640

Table 4. Single Speed (16 to 50 kHz sample rates) Common Clock

Frequencies

Serial Clock - SCLK

Pin 11, Input

Function:

Clocks individual bits of serial data into the SDATA pin. The

required relationship between the Left/Right

clock, serial clock and serial data is deﬁ ned by either the Mode

Control Byte in Control Port Mode or the

M0 - M4 pins in Hardware Mode. The options are detailed in

Figures 29-33

Left/Right Clock - LRCK

Pin 12, Input

Function:

The Left/Right clock determines which channel is currently being

input on the serial audio data input,

SDATA. The frequency of the Left/Right clock must be at the input

sample rate. Audio samples in

Left/Right sample pairs will be simultaneously output from the

digital-to-analog converter whereas

Right/Left pairs will exhibit a one sample period difference. The

required relationship between the

Left/Right clock, serial clock and serial data is deﬁ ned by the

Mode Control Byte and the options are de-

tailed in Figures 29-33

Serial Audio Data - SDATA

Pin 13, Input

Function:

Serial audio data is input on this pin. The selection of the Digital

Interface Format is determined by set-

tings of the Mode select as detailed in Figures 29-33. The data is

clocked into SDATA via the serial clock

and the channel is determined by the Left/Right clock. The

required relationship between the Left/Right

clock, serial clock and serial data is deﬁ ned by the Mode Control

Byte and the options are detailed inin

Figures 29-33

Soft Mute - MUTE

Pin 15, Input

Function:

The analog outputs will ramp to a muted state when enabled. The

ramp requires 1152 left/right clock cy-

cles in Single Speed, 2304 cycles in Double Speed and 4608

cycles in Quad Speed mode. The bias volt-

age on the outputs will be retained and MUTEC will go active at

the completion of the ramp period.

The analog outputs will ramp to a normal state when this function

transitions from the enabled to disabled

state. The ramp requires 1152 left/right clock cycles in Single

Speed, 2304 cycles in Double Speed and

4608 cycles in Quad Speed mode. The MUTEC will release

immediately on setting MUTE = 1.

The converter analog outputs will mute when enabled. The bias

voltage on the outputs will be retained

and MUTEC will go active during the mute period.

Mute DESCRIPTION

0 Enabled

1 Normal operation mode

Control Port / Hardware Mode Select - C/H

Pin 16, Input

Function:

Determines if the device will operate in either the Hardware Mode

or Control Port Mode.

C/H DESCRIPTION

0 Hardware Mode Enabled

1 Control Port Mode Enabled

Mute Control - MUTEC

Pin 17, Output

Function:

The Mute Control pin goes low during power-up initialization,

reset, muting, master clock to left/right clock

frequency ratio is incorrect or power-down. This pin is intended to

be used as a control for an external mute

circuit to prevent the clicks and pops that can occur in any single

supply system. Use of Mute Control is not

mandatory but recommended for designs requiring the absolute

minimum in extraneous clicks and pops.

Analog Ground - AGND

Pins 18 and 21, Inputs

Function:

Analog ground reference.

Differential Analog Outpus - AOUTR- , AOUTR+ and AOUTL- ,

AOUTL+

Pins 19, 20, 23 and 24, Outputs

Function:

The full scale differential analog output level is speciﬁ ed in the

Analog Characteristics speciﬁ cations table.

Analog Power - VA

Pin 22, Input

Function:

Power for the analog and reference circuits. Typically 5VDC.

QD61 : CS4397

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