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Marantz N1G Service Manual Page 43

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Terminal Function
1VDD Power Supply/Ground Power and ground for the input buffer and the core logic
2DQ0 Data Input/Output Data input/output are mutiplexed on the same pin
3DQ1 Data Input/Output Data input/output are mutiplexed on the same pin
4VSSQ Data Output Power/Ground Isolated power supply and ground for the output buffer
5DQ2 Data Input/Output Data input/output are mutiplexed on the same pin
6DQ3 Data Input/Output Data input/output are mutiplexed on the same pin
7VDDQ Data Output Power/Ground Isolated power supply and ground for the output buffer
8DQ4 Data Input/Output Data input/output are mutiplexed on the same pin
9DQ5 Data Input/Output Data input/output are mutiplexed on the same pin
10 VSSQ Data Output Power/Ground Isolated power supply and ground for the output buffer
11 DQ6 Data Input/Output Data input/output are multiplexed on the same pin
12 DQ7 Data Input/Output Data input/output are multiplexed on the same pin
13 VDDQ Data Output Power/Ground Isolated power supply and ground for the output buffer
14 L DQM Data Input/Output Mask Blocks data input when active
15 WE Write Enable Enables write operation and row precharge
16 CAS Column Address Strobe Latches column address on the positive going edge of the CLK at low
17 RAS Row Address Strobe Latches row address on the positive going edge of the CLK at low
18 CS Chip Select
Disables or enables device operation by masking or enabling all
inputs except CLK, CKE, and LDQM
19 BA Bank Select Address Selects bank to be activated during row address latch time
20 A10/AP Address Row/column addresses are multiplexed on the same pin
21 A0 Address Row/column addresses are multiplexed on the same pin
22 A1 Address Row/column addresses are multiplexed on the same pin
23 A2 Address Row/column addresses are multiplexed on the same pin
24 A3 Address Row/column addresses are multiplexed on the same pin
25 VDD Power Supply/Ground Power and ground for the input buffer and the core logic
26 VSS Power Supply/Ground Power and ground for the input buffer and the core logic
27 A4 Address Row/column addresses are multiplexed on the same pin
28 A5 Address Row/column addresses are multiplexed on the same pin
29 A6 Address Row/column addresses are multiplexed on the same pin
30 A7 Address Row/column addresses are multiplexed on the same pin
31 A8 Address Row/column addresses are multiplexed on the same pin
32 A9 Address Row/column addresses are multiplexed on the same pin
33 N. C No Connection No connect pin
34 CKE Clock Enable Masks system clock to freeze operation from the next clock cycle
35 CLK System Clock Active on the positive going edge to sample all inputs
36 U DQM Data Input/Output Mask Blocks data input when active
37 N. C/RFU NC/Reserved No connect pin
38 VDDQ Data Output Power/Ground Isolated power supply and ground for the output buffer
39 DQ8 Data Input/Output Data input/output are multiplexed on the same pin
40 DQ9 Data Input/Output Data input/output are multiplexed on the same pin
41 VSSQ Data Output Power/Ground Isolated power supply and ground for the output buffer
42 DQ10 Data Input/Output Data input/output are multiplexed on the same pin
43 DQ11 Data Input/Output Data input/output are multiplexed on the same pin
44 VDDQ Data Output Power/Ground Isolated power supply and ground for the output buffer
45 DQ12 Data Input/Output Data input/output are multiplexed on the same pin
46 DQ13 Data Input/Output Data input/output are multiplexed on the same pin
47 VSSQ Data Output Power/Ground Isolated power supply and ground for the output buffer
48 DQ14 Data Input/Output Data input/output are multiplexed on the same pin
49 DQ15 Data Input/Output Data input/output are multiplexed on the same pin
50 VSS Power Supply/Ground Power and ground for the input buffer and the core logic
Pin Name FunctionPin No. Symbol
IC402 : 16M SDRAM (EM636165TS-7 etc)
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