Marantz DV4100 User Manual Page 90

  • Download
  • Add to my manuals
  • Print
  • Page
    / 143
  • Table of contents
  • TROUBLESHOOTING
  • BOOKMARKS
  • Rated. / 5. Based on customer reviews
Page view 89
34ASD-1 7.
Electrical diagrams and PWB’s
Memory
VDDQ
LCBR
DATA INPUT
REGISTER
PROGRAMMING
LRAS
LCBR
512Kx16
BANK
SELECT
OUTPUT BUFFER
VSS VSSQ
TIMING REGISTER
NC
512Kx16
ADDRESS REGISTER
LCKE
BURST LENGTH
LATENCY &
DECODER
COLUMN
LWCBR
LCAS
LWE
REGISTER
COL. BUFFER
LQDM
ROW DECODER
REFRESH COUNTER
ROW BUFFER
LDQM
LWE
I/O CONTROL
SENSE AMP
LRAS
VDD VDDQ
LCBR
DATA INPUT
REGISTER
PROGRAMMING
LRAS
LCBR
512Kx16
BANK
SELECT
OUTPUT BUFFER
VSS VSSQ
TIMING REGISTER
NC
512Kx16
ADDRESS REGISTER
LCKE
BURST LENGTH
LATENCY &
DECODER
COLUMN
LWCBR
LCAS
LWE
REGISTER
COL. BUFFER
LQDM
ROW DECODER
REFRESH COUNTER
ROW BUFFER
LDQM
LWE
I/O CONTROL
SENSE AMP
LRAS
VDD
H
I
E
F
G
H
3412 E5
3413 F5
3414 F5
3415 F5
3416 G5
3418 E4
3402 E1
3403 F8
3404 F11
123
7400-A E2
7400-B F2
7400-C I6
78910
5400 A3
5402 I9
5403 I12
456
13 14
A
B
C
D
SDRAM Interface
789101112
F428 I8
F430 H2
F431 H1
F432 G5
F434 F5
F435 F5
SYSTEM DATA Bus
TOP
RAM/ROM Interface
2400 B3
2401 C9
2402 C10
2403 C12
I
A
B
C
D
E
F
G
3405 F5
3406 I7
3407 I3
3409 H7
3410 I6
2417 H3
2418 I10
2419 I13
2420 I13
3400 C1
3401 C2
OPTION
OPTION
7400-D E3
7401 C6
7402 H2
7403 H3
7404 D9
7405 D12
7406 B3
F406 E2
F415 G8
F416 G11
F419 I10
11 12 13 14
1
MEMORY PART
BOTTOM
SYSTEM ADDRESS Bus
23456
OPTION
OPTION
OPTION
OPTION
F420 I13
F421 A3
F422 C2
F423 C2
F424 C2
F425 C2
2404 C13
2405 B6
2406 C9
2407 C10
2408 C12
2409 C13
2410 C9
2411 C10
2412 C12
2413 C13
2414 H7
2415 E1
2416 H2
3404
10K
2410
100n 100n
2411
+5V_DS
VDD_MEM2
10K
3405
10K
3402
2417
100n
2401
100n
13 38 44
26 50 4 10 41 47
WE_15
VDD_MEM2
6
DQ4 8
DQ5 9
DQ6 11
DQ7 12
39DQ8
40DQ9
DQMH36
14 DQML
33
37
RAS_17
125 7
A8
32 A9
BA19
CAS_16
34 CKE
35 CLK
18 CS_
DQ0 2
DQ1 3
42DQ10
43DQ11
45DQ12
46DQ13
48DQ14
49DQ15
DQ2 5
DQ3
MT48LC1M16A1TG
7404
21 A0
22 A1
A1020
23 A2
24 A3
27 A4
28 A5
29 A6
30 A7
31
74HCT1G04
7403
2
3
NC
1
5
4
100n
2416
2408
100n
2400
100n
+5V_DS
5400
100MHZ
100n
2412
+5V_DS
22R
3407
74HCT1G79
7402
2
1
3
4
5
+3V3
+5V_DS
F430
100u
2418
+3V3
F424
+5V_DS
3418
F423
2404
100n
VDD_MEM2
100MHZ
5402
74HCT00D
7400-A
1
2
7
14
3
2414
100n
VDD_MEM2
+5VOSC
F431
F416
RD_
19
RESET_|STROBE_
3
SCL|SCL-IN
2
SDA|SDA-OUT
20
VDD
10
VSS
18
WR_
3401
100R
6
A0
1
CLK
17
CS_
7
DB0
8
DB1
9
DB2
11
DB3
12
DB4
13
DB5
14
DB6
15
DB7
4
IACK_|SDA-IN
5
INT_|SCL-OUT
16
VDD_MEM2
PCF8584T
7406
F415
100n
2403
100n
2402
3410
100n
2406
3409
VDD_MEM
+5Vstby
F434
100n
2405
VDD_MEM
F432
3414
3415
VDD_MEM
3413
74HCT00D
7400-C
9
10
7
14
8
3412
F419
100R
3406
F425
3416
41 47
15 WE_
39
DQ9 40
36 DQMH
DQML14
33
37
17 RAS_
1 25 7 13 38 44
26 50 4 10
35
CS_18
2DQ0
3DQ1
DQ10 42
DQ11 43
DQ12 45
DQ13 46
DQ14 48
DQ15 49
5DQ2
6DQ3
8DQ4
9DQ5
11DQ6
12DQ7
DQ8
A021
A122
20 A10
A223
A324
A427
A528
A629
A730
A831
A932
19 BA
16 CAS_
CKE34
CLK
7405
MT48LC1M16A1TG
F422
F421
100n
2415
100n
2409
DQ8
18
DQ9
14
OE_
1
RESET_
23
VCC
13
VSS1
32
VSS2
44
WE_
BYTE_
12
CE_
15
DQ0
17
DQ1
20
DQ10
22
DQ11
25
DQ12
27
DQ13
29
DQ14
31
DQ15|A-1
19
DQ2
21
DQ3
24
DQ4
26
DQ5
28
DQ6
30
DQ7
16
A12
37
A13
36
A14
35
A15
34
A16
3
A17
2
A18
43
A19
9
A2
8
A3
7
A4
6
A5
5
A6
4
A7
42
A8
41
A9
33
Am29LV160BT
7401
11
A0
10
A1
40
A10
39
A11
38
F420
47u
2419
2413
100n
12
13
7
14
11
F428
+5V_DS
7400-D
74HCT00D
VDD_MEM
F435
100R
3400
2420
47u
2407
100n
4
5
7
14
6
7400-B
74HCT00D
F406
VDD_MEM
3403
10K
100MHZ
5403
27M_CLKOUT
WAIT
SCL_EXE
SDA_EXE
CE1
DQMU
DQML
CE1
A1
D0
D1
D2
D3
D4
D5
D6
D7
RWN
CLK_8MHz
DTACKn
IRQ_I2C
RESET_I2C
AUXCLK
27M_CLK1
CLK_8MHz
CASN
CLK
CSN2
RASN
WEN
DTACKn
AD10
AD11
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD0
AD1
AD10
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD11
AD9
CASN
CLK
CSN1
DQMU
DQML
RASN
WEN
AD0
AD1
3104 123 4268.4
PB 4268 ASD1
MONO-BOARD
CL06532065_041.eps
290500
OPTION = NOT USED FOR FUTURE APPLICATION: I
2
C FROM MASTER TO SLAVE FOR SYSTEMS / COMBI'S
Page view 89
1 2 ... 85 86 87 88 89 90 91 92 93 94 95 ... 142 143

Comments to this Manuals

No comments